Certain known computer-aided design (CAD) techniques have been developed to aid in the synthesis of integrated circuits including integrated logic circuits. Such techniques have included simulating the operation of proposed circuit designs and producing netlists (detailed circuit specifications including circuit components, also referred to as cells, from a pre-defined library, and interconnections, also referred to as nodes, between the cells), as with Microcap, Spice or similar programs. Such techniques have further included generating silicon layouts including routing from netlists of proposed circuit designs and developing sets of semiconductor masks from the silicon layout for later utilization in semiconductor chip production equipment, as with a silicon compiler.
The aforementioned techniques have been utilized in computer-aided integrated circuit design systems for the synthesis of integrated logic circuits; however, with respect to digital multiplier design, manual intervention is frequently required by multiple design specialists within a circuit design team.
Design intervention is time consuming and requires specialists who are highly knowledgeable both in circuit design and in the placement and routing of integrated circuits.
Therefore, there is a need for an automated design method and system which generates a digital multiplier circuit design and layout from design specifications inserted at the logic level without the need for design intervention.